The present invention relates to solid-state imaging apparatus, and more particularly relates to a solid-state imaging apparatus using an amplification-type MOS sensor.
In recent years, those solid-state imaging apparatus employing an amplification-type MOS sensor as the solid-state imaging apparatus are used as a solid-state imaging apparatus of low power consumption for mobile equipment or are mounted on a high-resolution electronic still camera. While the latest solid-state imaging apparatus using amplification-type MOS sensor generally employ progressive scanning where pixel signals are sequentially read out, it is also an requirement in the above described electronic still camera to rapidly read image signals of a relatively low resolution for example for a small frame to be used in a viewfinder or monitor. For this reason, there has been proposed a processing for reducing the number of image data by mixing a plurality of image signals in a horizontal or vertical direction within the solid-state imaging apparatus.
FIG. 1 is a circuit diagram showing an example of such solid-state imaging apparatus having a means for mixing a plurality of pixel signals in a horizontal direction disclosed for example in Japanese Patent Application Laid-Open 2006-14107. The solid-state imaging apparatus shown in FIG. 1 includes: a pixel section 1 where unit pixels P11 to P44 are two-dimensionally arranged in rows and columns; a vertical scanning circuit 2 for selecting a row to be read out of the pixel section 1; a current supply section 3 for supplying a bias current to the pixel section 1; a noise suppressing section 4 for suppressing noise component contained in output signal of the pixel sectional; a horizontal select switch section 5 for outputting signals suppressed of noise; a horizontal scanning circuit 6 for selecting column to be read through the horizontal select switch section 5; an output line 7; and a mode control section 8, for determining operation timing of the noise suppressing section 4 and horizontal scanning circuit 6. It should be noted that the pixel section 1 in the illustrated example is shown as a portion consisting of 4×4 pixel arrangement.
The unit pixel P11 to P44 includes: a photodiode PD1 serving as photoelectric conversion section; a reset transistor M1 for resetting detection signal of the photodiode PD1; an amplification transistor M2 for amplifying signal of the photodiode PD1; and a row select transistor M3 for selecting the unit pixels of each row.
A row to be read out of the pixel section 1 is then selected by power supply line VR1 to VR4, row reset line φRST1 to φRST4, and row select line φROW1 to φROW4 which are outputs of the vertical scanning circuit 2 so that the pixel signals of the unit pixels P11 to P44 are read out row by row.
At the noise suppressing section 4, a noise suppressing circuit CDS1 to CDS4 consisting of a sampling transistor M21 to M24, clamping transistor M31 to M34, clamping capacitor C31 to C34, and holding capacitor C41 to C44 is provided for each column, and in addition horizontal mixing transistors. M42 and M43 for connecting clamp output lines CL11, CL12, and CL13 are provided.
The drive operation at the time of horizontal mixing in the solid-state imaging apparatus having such construction will now be described by way of a timing chart shown in FIG. 2. A description will be given below with noticing the operation of the pixels of first to third rows from the left side in the case where a first row from the upper side of the pixel section 1 is selected by the vertical scanning circuit 2. At first, drive timing at the time of horizontal mixing operation is set to the noise suppressing section 4 and horizontal scanning circuit 6 by control signal of the mode control section 8.
Subsequently, row select line signal φROW1 is driven to H level to turn ON each row select transistor M3 of the unit pixels P11 to P13 so that signal voltages of each photodiode PD1 contained in unit pixels P11 to P13 are respectively outputted to vertical signal lines V11 to V13 through the amplification transistor M2. At this time, the signal voltages on the vertical signal lines V11 to V13 are respectively supposed as VV11-SIG to VV13-SIG 
Here, sample control line signal φSH and clamp control line signal φCL are driven to H level at the noise suppressing section 4 so that the sampling transistors M21 to M23 and clamping transistors M31 to M33 are turned ON. The clamp output lines CL11 to CL13 are thereby set to a voltage value VREF of a reference voltage line REF so that difference voltages as shown in the following expressions (1) to (3) are accumulated at the clamping capacitors C31 to C33. It should be noted that, since the horizontal mixing transistors M42 and M43 are being turned ON at this time by driving horizontal mixing control line signal φAV−H to H level, the clamp output lines CL11 to CL13 are connected to one another.Difference voltage accumulated at C31: VV11-SIG−VREF  (1)Difference voltage accumulated at C32: VV12-SIG−VREF  (2)Difference voltage accumulated at C33: VV13-SIG−VREF  (3)
Next, the clamp control line signal φCL is changed to L level to bring the clamp output lines CL11 to CL13 to their high-impedance state. In this condition, then, after driving row reset line signal φRST1 to H level; the signal φRST1 is brought to L level again. The reset voltages of each photodiode PD1 contained in the unit pixels P11 to P13 are thereby respectively outputted to the vertical signal lines V11 to V13 through the amplification transistor M2. At this time, supposing VV11-RST to VV13-RST τ respectively as reset voltages on the vertical signal lines V11 to V13 and ΔVV11 to ΔVV13 respectively as difference voltages between the signal voltages and the reset voltages of the vertical signal lines V11 to V13, the relationships of the following expressions (4) to (8) are obtained by the conservation law of electric charge, since the clamp output lines CL11 to CL13 are in their high-impedance state.ΔVV11−ΔVCL11=ΔQC31/C31  (4)ΔVV12−ΔVCL12=ΔQC32/C32  (5)ΔVV13−ΔVCL13=ΔQC33/C33  (6)ΔVCL11=ΔQ/(C41+C42+C43)  (7)ΔQ=ΔQC31+ΔQC32+ΔQC33  (8)where: ΔVCL11(=ΔVCL12=ΔVCL13) is amount of change of the clamp output line voltage VCL11(=VCL12=VCL13); ΔQC31 to ΔQC33 is amount of change of electric charge at the clamping capacitors C31 to C33; and ΔQ is a total change amount of electric charge at the holding capacitors C41 to C43.
Further, the following expressions (9), (10) are obtained by rearranging (4) to (8) with supposing that the clamping capacitors C31 to C33 each have the same capacitance value CCL and that the holding capacitors C41 to C43 each have the same capacitance value CSH.
                              Δ          ⁢                                          ⁢                      V                          CL              ⁢                                                          ⁢              11                                      =                  [                                    {                              CCL                /                                  (                                      CCL                    +                    CSH                                    )                                            }                        ×                                          (                                                      Δ                    ⁢                                                                                  ⁢                                          V                                              V                        ⁢                                                                                                  ⁢                        11                                                                              +                                      Δ                    ⁢                                                                                  ⁢                                          V                                              C                        ⁢                                                                                                  ⁢                        12                                                                              +                                      Δ                    ⁢                                                                                  ⁢                                          V                                              V                        ⁢                                                                                                  ⁢                        13                                                                                            )                            /              3                                ]                                    (        9        )                                                                                    V                                  CL                  ⁢                                                                          ⁢                  11                                            =                            ⁢                                                V                  REF                                +                                  Δ                  ⁢                                                                          ⁢                                      V                                          CL                      ⁢                                                                                          ⁢                      11                                                                                                                                              =                            ⁢                                                V                  REF                                +                                  [                                                            {                                              CCL                        /                                                  (                                                      CCL                            +                            CSH                                                    )                                                                    }                                        ×                                                                                                                                        ⁢                                                (                                                            Δ                      ⁢                                                                                          ⁢                                              V                                                  V                          ⁢                                                                                                          ⁢                          11                                                                                      +                                          Δ                      ⁢                                                                                          ⁢                                              V                                                  V                          ⁢                                                                                                          ⁢                          12                                                                                      +                                          Δ                      ⁢                                                                                          ⁢                                              V                                                  V                          ⁢                                                                                                          ⁢                          13                                                                                                      )                                /                3                            ]                                                          (        10        )            
Accordingly, even when the thresholds of the amplification transistors M2 contained in the unit pixels P11 to P13 are different from one another due to manufacturing variance, the threshold components are contained in both the signal voltage and the reset voltage.
For this reason, by obtaining a difference voltage between these, it is possible to obtain an output where the threshold variance of amplification transistor M2 is canceled. In addition, at the same time of completion of the noise suppressing operation of pixel signals of the unit pixels P11 to P13, the mixing operation of the pixel signals is also ended.
After that, by bringing the sample control line signal φSH to L level to turn OFF the sampling transistors M21 to M23, the pixel section 1 and the noise suppressing section 4 are disconnected from each other. Further, the horizontal mixing control line signal φAV−H is brought to L level to turn OFF the horizontal mixing transistors M42 and M43, thereby respectively disconnecting the clamp output lines CL11 to CL13 which have been connected to one another. Subsequently, the row select line signal φROW1 is changed to L level to respectively disconnect the connection between the unit pixels P11 to P13 and the vertical signal lines V11 to V13.
Signal are read from the noise suppressing section. 4 to the output line 7 as follows. First, the reset control line signal φRS is driven to H level to turn ON an output resetting transistor M111 so as to set the output line 7 to the voltage value VHREF of an output reference voltage line HREF, and the reset control line signal φRS is then switched to L level again to effect a reset operation of the output line. Subsequently, signals are read out from the noise suppressing section 4 to the output line 7 through the horizontal select switch section 5 which is selected by the horizontal scanning circuit 6. Here, by outputting horizontal select pulses φH1, φH4 from the horizontal scanning circuit 6, the horizontal select switch section 5 is operated with skipping two columns so as to read the mixed signals out to the output line 7 only from: the holding capacitors C41 and C44. The number of image data thereby becomes ⅓.
FIG. 3 shows an example of read method of OB pixels in a solid-state imaging apparatus capable of effecting thinned-out read disclosed for example in Japanese Patent Application Laid-Open hei-9-163236. In this method as shown in FIG. 3, all pixel signals are read out from the horizontal OB pixel region even at the time of subsampled read in order to achieve an optimum OB clamp operation to effect stable imaging against changes in ambient environment such as temperature. By then obtaining an average value of these OB pixel signals in the horizontal direction, an optimum OB clamp operation is effected.